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TitleLow_power_ver_wp Cadence Cpf Ver Important
TagsSimulation Formal Verification System On A Chip Analogue Electronics Emulator
File Size964.4 KB
Total Pages16
Document Text Contents
Page 1

W
H

IT
E

P
A

P
E

R POWER-AWARE VERIF ICATION
SPANS IC DESIGN CYCLE
A PLAN-TO-CLOSURE APPROACH HELPS
ENSURE SIL ICON SUCCESS

JOHN DECKER, NEYAZ KHAN, AND RICHARD GOERING, CADENCE DESIGN SYSTEMS

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INTRODUCTION

The mandate to reduce system power consumption and design energy-efficient ICs has led to the
increasing use of low-power IC design techniques. In addition to well-established techniques like
clock gating, IC designers today are using advanced techniques such as power shutoff, back body
biasing, and dynamic voltage and frequency scaling (DVFS). More and more chips have multiple
operating modes as well as multiple power domains with different, and perhaps dynamically
variable, voltage levels.

The central problem with low-power verification is the explosion in scope and complexity caused by
low-power design techniques. Some chips today have 20 to 50 power domains and hundreds of
power modes. As a result, chips may have thousands or tens of thousands of possible power
states. Verification engineers must ensure that the chip functions correctly in each state that could
plausibly occur, and that all transitions between states are properly handled.

Because of this complexity, verification planning is essential for low-power designs. An ad-hoc
approach is not likely to succeed. The verification effort should start with a measurable, executable
plan that sets forth goals and priorities. This plan should guide verification efforts all the way to
verification closure, which occurs when goals are met. Along the way, low-power design effects
must be continuously analyzed and verified from the systems level to GDSII.

With low-power design, verification engineers face new challenges such as the following:

• Ensuring that the system-level architecture is using the power modes efficiently and correctly.

• Verifying the interactions between different power domains.

• Verifying the transitions between different power modes and states.

• Modeling low-power structures that do not exist in RTL.

• Ensuring that isolation, state retention, and power shutoff are handled properly, and that the
device can power on correctly within a given time period.

Different power optimization techniques have differing impacts on verification. For example, clock
gating has a minor impact, multiple power domains and multi-Vt libraries have a moderate impact,
and power shutoff, DVFS, and multiple operating modes have a major impact (see Figure 1).

PCM 0.7V

1.1V

0.7VPCM

CLK

CPU

0.7V or
1.1V

0.7V

PCM 1.1V or
shutoff

SW

Im
p

a
ct

o
n

V
e
ri

fi
ca

ti
o

n

• Clock Gating
• Synthesis opto

• Multiple Power domains
• Multi-Supply voltage
• Multi-VT library
• Advanced opto

• Power shutoff
• Dynamic voltage & freq.
• HW & SW control
• Multiple operating modes
• Complex domain interactions

Figure 1: Some advanced low-power design techniques have a profound impact on verification.

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Cadence® Encounter® Conformal® Low Power provides automated checks that can ensure that the
specified power intent is complete and correct. It also provides a “linting” capability that checks for
proper syntax.

Encounter Conformal Low Power is used throughout the verification flow. Early checks might
include tests for missing isolation or level shifter cells, tests for power control functionality, and
checks that state retention and isolation control signals are driven correctly by domains that remain
powered up. Later on, post-placement checks can ensure that gate power pins are hooked to the
appropriate power rails, that always-on cells are appropriately powered, and that there are no
“sneak” paths from power-down domains back to logic.

Encounter Conformal Low Power also provides logical equivalence checking (LEC), and that too can
be used throughout the RTL-to-GDSII verification flow. Equivalence checking can prove that
isolation and state retention cells have been inserted correctly, even though these cells are in the
CPF file rather than the RTL source. Figure 5 shows how static checking and LEC are used during
the low-power verification flow.

Encounter
Conformal

(Static checking)

Encounter
Conformal

(Equivalence checking)

CPF Quality
and Functional

Checking

RTL-to-Gate
Functional

Comparison

Gate-to-Gate
Functional

Comparison

Structural and
Rules Checking

Structural and
Rules Checking

RTL & CPF

Synthesis

Gate Netlist

Place/Route

Gate Netlist

Design

Figure 5 – Encounter Conformal Low Power can be used throughout the verification flow.

LOW-POWER SIMULATION

After CPF is used to capture power intent, design teams can simulate behavior such as power
shutoff, isolation, and retention, and observe the effects. Because this information is specified in
the CPF file, not the RTL, no RTL changes are required. Given the information in the CPF file and
the appropriate test vectors, a CPF-aware simulator such as the Incisive Unified Simulator can
exercise the power shutdown and startup sequences for the design.

CPF commands that are understood by Incisive Unified Simulator 6.2 and above include:

• Power domain definition – different power domains and operation supply voltage

• Power shutoff property specification – isolation, retention, and power-down triggers

• Level shifters between power domains that run at different voltages

Low power simulation should be enabled for all simulation runs. If power-aware simulation is run
only in tests and scenarios that are designed to test power-aware features, simulations may not
catch errors that unexpectedly trigger low-power features. With Incisive Unified Simulator there is
virtually no run-time impact in running with low power enabled, and no reason not to do so.

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POWER-AWARE VERIF ICATION SPANS IC DESIGN CYCLE 9

Figure 7 shows the types of simulation that should be run, what device under verification (DUV)
representation they use, and what else the verification environment might include, such as
coverage, the Cadence® Incisive® Palladium® Accelerator/Emulator, Cadence® Incisive® Software
Extensions, and Cadence® Incisive® Formal Verifier.

Coverage
DB Assertion

DB

Incisive
Formal Verifier

RTL Sim

RTL CPF

Multiple Modes of DUVVerification Environment

Verification
Management

Behavioral Simulation

Palladium

TLM

C-Models

RTL Sim

System Simulation

RTL Sim

Block Simulation

Palladium

CPU-Models

Incisive Plan-to-Closure
Methodology

VIP

Assertion

Coverage

Incisive Software
Extensions

HW/SW

Figure 6 – Types of simulation used in low-power verification

The role of behavioral simulation is to verify the system and software architecture of the design. In
the low power environment, there are two key tasks:

• Functionally verify the power architecture from a systems perspective

• Ensure that the power architecture is used efficiently by the system software and hardware

For the first task, the most common sources of functional error are the interfaces between power
domains and the transitions between power modes, especially when power shutoff is used.
Ensuring that all power modes and transitions have been exercised is the only way to verify that
these interfaces are defined correctly. For the second task, the verification environment needs to
ensure that all the available power modes are used, and that the low power modes are used as
often as expected.

Verifying these issues requires extensive simulations with high-level models. This includes transac-
tion level models (TLMs), C language models, and possibly emulation technology. A fairly simple
model of the power architecture is probably sufficient. RTL simulation will require a much more
detailed model.

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POWER-AWARE VERIF ICATION SPANS IC DESIGN CYCLE 15

STANDBY MODE

Standby mode is a special case of DVFS. This mode reduces voltages to a level that’s still high
enough to retain the states of all state elements in a domain, but too low to calculate any new
values. Full power shutoff, in contrast, turns off all dynamic power and all leakage power except
for state retention cells. Standby mode provides a good savings in leakage power without the need
for state retention. This simplifies the complex problem of determining the exact state retention
registers that are required to restore state. Since the full state is retained, the power-up sequence
is typically much faster than a PSO cycle, especially if the PSO does a full reset on power up.

From a verification point of view, when an input changes in standby mode, everything downstream
from that input is corrupted. Incisive Unified Simulator 8.2 detects standby voltages, automatically
checks for unintended input toggles, and automatically propagates X states as required.

IP DESIGN AND REUSE FOR LOW POWER

The best way to design an IP block that will be used in a low-power environment is to provide a
CPF file that defines power behavior for the block. The block should also come with a detailed
specification of the requirements needed to use these low-power features, and include assertions
and tests to verify the implementation.

Blocks are sometimes used in power environments they were not designed for. In such cases, it is
up to the IP integrator to ensure that the block operates properly. Most low-power design
techniques won’t perturb the block, but with PSO, the user needs to ensure that the state retention
and restoration process will work properly, and define the behavior of assertions.

Blocks that will be reused in a low-power environment should come with the following infor-
mation:

• State retention and restoration policy

• I/O requirements, including input isolation requirements

• Assertion behavior when power is shut off

• Coverage information

Another ideal deliverable is a compliance checklist that includes a verification plan, a set of
coverage items and assertions, and a set of test cases that validate whether the part is being used
in an expected manner.

CONCLUSION

Functional verification is a difficult task – and low-power design makes it even more difficult. With
today’s low power design techniques, ICs may have dozens or hundreds of different power modes
and domains. The IC must function correctly in every possible power state, and transitions between
power states must be correct. Power shutoff (PSO) and dynamic voltage and frequency scaling
(DVFS) are particularly problematic from a verification standpoint.

A plan-to-closure methodology, complemented by power-aware verification tools and a common
way of expressing power intent, can go a long ways towards easing the low-power verification
challenge. Such a methodology begins with a verification plan based on the low-power archi-
tecture. The plan defines verification closure and describes how to measure it through coverage
metrics.

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© 2009 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Conformal, Encounter, Incisive, Palladium, and VoltageStorm are
registered trademarks of Cadence Design Systems, Inc.

20917 05/09 RG/DM/PDF

The verification plan should describe all of the power modes and domains, and explain the features
available in each power mode. Addressing both system-level and domain-level verification, it
provides scenarios, tests, transactions and features for each power mode. A Common Power Format
(CPF) file, which is separate from the RTL code, then conveys power intent to all of the downstream
tools in the verification flow.

Every tool in the verification toolbox can contribute to low-power verification. Static, formal
checking can make sure the power intent is complete and correct. Simulators can read the CPF file
and verify the power intent. Emulation, formal property checking, and assertion-based verification
can all play an important role. But all these tools must be used with an awareness of low-power
features such as PSO and DVFS.

Anyone contemplating low-power design must also consider the challenge of low-power verifi-
cation. Fortunately, help is available in the form of verification planning, a common power format,
and power-aware verification tools. A plan-to-closure methodology and an integrated suite of tools
can make low-power verification a manageable challenge.

For more information

contact Cadence sales at:

+1.408.943.1234

or log on to:

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